DS3106LN+【PDF 13/92 页】IC TIMING LINE CARD 64-LQFP

DS3106

Digital PLLs have two key benefits: (1) stable, repeatable performance that is insensitive to process variations,

temperature, and voltage; and (2) flexible behavior that is easily programmed through the configuration registers.

DPLLs use digital frequency synthesis (DFS) to generate various clocks. In DFS a high-speed master clock

(204.8MHz) is multiplied up from the 12.800MHz local oscillator clock applied to the REFCLK pin. This master

clock is then digitally divided down to the desired output frequency. The DFS output clock has jitter of about 1ns pk-

pk.

The analog PLLs filter the jitter from the DPLLs, reducing the 1ns pk-pk jitter to less than 0.5ns pk-pk and 60ps

RMS, typical, measured broadband (10Hz to 1GHz).

The DPLLs in the device are configurable for many PLL parameters including bandwidth, damping factor, input

frequency, pull-in/hold-in range, and more. No knowledge of loop equations or gain parameters is required to

configure and operate the device. No external components are required for the DPLL or the APLLs except the

high-quality local oscillator connected to the REFCLK pin.

The T0 DPLL has a full free-run/locked/holdover state machine and full programmability.

7.7.1 T0 DPLL State Machine

The T0 DPLL has three main timing modes: locked, holdover, and free-run. The control state machine for the T0

DPLL has states for each timing mode as well as three temporary states: prelocked, prelocked 2, and loss-of-lock.

The state transition diagram is shown in Figure 7-2. Descriptions of each state are given in the paragraphs below.

During normal operation the state machine controls state transitions. When necessary, however, the state can be

forced using the T0STATE field of the MCR1 register.

Whenever the T0 DPLL changes state, the STATE bit in MSR2 is set, which can cause an interrupt request if

enabled. The current T0 DPLL state can be read from the T0STATE field of the OPSTATE register.

7.7.1.1 Free-Run State

Free-run mode is the reset default state. In free-run all output clocks are derived from the 12.800 MHz local

oscillator attached to the REFCLK pin. The frequency of each output clock is a specific multiple of the local

oscillator. The frequency accuracy of each output clock is equal to the frequency accuracy of the master clock,

which can be calibrated using the MCLKFREQ field in registers MCLK1 and MCLK2 (see Section 7.3). The state

machine transitions from free-run to the prelocked state when at least one input clock is valid.

7.7.1.2 Prelocked State

If phase lock (see Section 7.7.5) is achieved for 2 seconds during this period, the state machine transitions to

locked mode. If the selected reference becomes inactive for 2 seconds then the state machine transitions back to

the free-run state.

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